A student from various disciplines can Apply. Interested and eligible candidates can read more details below.
| Company Name | Microsoft |
| Post Name | Physical Design Engineer |
| No of Posts | Various |
| Job Location | Bangalore |
| Last Date to Apply | 12/03/2023 |
Microsoft Recruitment 2023 Eligibility Details
Qualifications
- BS/MS in Electrical or Computer Engineering
- 3+ years of experience in semiconductor design.
- Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Preferred Qualifications:
- Large SoC design tape-out experience in the latest foundry process nodes.
- Excellent project management skills and ability to juggle multiple projects at once.
- Strong understanding of constraints generation, STA, timing optimization, and timing closure.
- In-depth understanding of design tradeoffs for power, performance, and area.
- Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.
- Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Fusion Compiler, Innovus etc.
- Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise.
- Strong problem-solving and data analysis skills
- Strong automation skills using scripting languages such as Perl, TCL, Python.
| Apply for Pwc | Apply for oracle |
| Apply for Zoho | Apply for Infosys |
| Apply for Wipro | Apply for Genpact |
| Apply for Apple | Apply for siemens |
| Apply for Volvo | Apply for Microsoft |
| Apply for Deloitte | Apply for solugenix |
| Apply for Logitech | Apply for Accenture |
| Apply for Mindtree | Apply for Capgemini |
Responsibilities
- Own and drive floor planning and design planning for optimizing large sub-chips for Power, Performance and Area
- Own and drive execution from synthesis to place and route of large sub-chips and/or full chip through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
- Have close collaboration with RTL team to help drive and resolve design issues related to full chip and block closure.
- Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
- Implement robust clock distribution solutions using appropriate methods that meet design requirements.
- Make good independent technical trade-offs between power, area, and timing.
- Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.
Selection Process for Microsoft Recruitment 2023
Selection Will be Based either Written Exam/Interview
How to Apply Microsoft Recruitment 2023 at microsoft.com?
Interested and Eligible Candidates can apply the post on or before last date
join our Official You tube: Click Here
Join our Official Linked in: Click Here
Join our Official Twitter: Click Here
